Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic die mounted to a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The die also typically includes bond pads electrically coupled to the functional features. The bond pads are coupled to pins or other types of terminals that extend outside of the protective covering for connecting the microelectronic die to buses, circuits and/or other microelectronic assemblies.
In one conventional arrangement shown in FIG. 1A, a die 20 is mounted to a printed circuit board (PCB) 30 with an adhesive layer 23. The die 20 has internal functional features (not shown in FIG. 1A) coupled to die bond pads 33a on an external surface of the die 20. Each die bond pad 33a is connected with a wire bond 34 to a corresponding PCB bond pad 33b on a surface of the PCB 30 facing away from the die 20. Accordingly, the PCB 30 has a central aperture 31 that receives the wire bonds 34 and is aligned with the die bond pads 33a. The PCB bond pads 33b are connected to solder ball pads 32 with circuitry (not shown) internal to the PCB 30 for coupling the die 20 to other devices or circuit elements.
To encapsulate the die 20, the die 20 and the PCB 30 are positioned in a mold apparatus 40 by clamping a portion of the PCB 30 between an upper mold portion 41 and a lower mold portion 42. The die 20 is aligned with an upper cavity 43 in the upper mold portion 41 and the wire bonds 34 are aligned with a lower cavity 44 in the lower mold portion 42. A mold compound 60, such as an epoxy mold compound, is injected into the mold cavities 43 and 44, and the encapsulated die 20 and PCB 30 are then removed from the mold apparatus 40. The periphery of the PCB 30 is trimmed to form the device package 50 shown in FIG. 1B. Solder balls 35 are attached to the solder ball pads 32 for coupling the device package 50 to other devices, such as another PCB 30a having bond pads 33c aligned with the solder balls 35.
One drawback with the approach described above with reference to FIGS. 1A-1B for packaging the die 20 is that the mold apparatus 40 can allow the mold compound 60 to adhere to the solder ball pads 32 during the encapsulation process. For example, unclamped regions 45 of the lower mold portion 42 directly adjacent to the solder ball pads 32 are not directly supported by any corresponding structure of the upper mold portion 41 when the mold portions 41 and 42 are clamped together (by contrast, adjacent clamped regions 46a of the lower mold portion 42 are subjected to a direct normal force by corresponding clamped regions 46b of the upper mold portion 41). Accordingly, the PCB 30 can flex away from the unclamped region 45 and can allow the mold compound 60 to cover the solder ball pads 32. The mold compound 60 on the solder ball pads 32 can prevent the solder balls 35 from properly adhering to the solder ball pads 32, and can accordingly interfere with a secure electrical connection between the device package 50 and other devices or circuit elements to which the package 50 is attached. Furthermore, the flexing PCB 30 can place stresses on the die 20 that can potentially damage the die 20.
One approach to addressing the foregoing drawback is to form a trench in the lower mold portion 42 adjacent to the solder ball pads 32 for collecting any mold compound 60 that approaches the solder ball pads 32. However, such trenches are not always effective and, as the dies 20 become smaller, it can be difficult to find space between the lower cavity 44 and the solder ball pads 32 in which to position such a trench.
Another drawback with the conventional approach described above with reference to FIGS. 1A-1B is that it can be difficult to transfer heat away from the die 20 through the mold compound 60. Accordingly, the die 20 can overheat, which can limit the performance and/or the expected life of the die 20.
Still another drawback with the conventional arrangement described above with reference to FIGS. 1A-1B is that it may not be convenient to stack the device packages 50 on top of each other, a technique that can increase the number of packages 50 provided per unit area in compact electronic devices. In one conventional stacked arrangement, notches are cut into the edges of the PCB 30 of each package 50 and a jig is used to align the notches of a first package with the notches of a second package stacked on the first package. However, this arrangement can be cumbersome and can cause damage to the dies 20, for example, if the jig is handled improperly.